July 26, 2024

PyIgH : A unified architecture of IgH EtherCAT Master based on Python considering hard real-time  constraints

Prof. Delgado collaborated with the Embedded Systems Laboratory of Seoul National University of Science and Technology (Seoul, South Korea) to publish a joint research article in Microprocessors and Microsystems (SCIE, Q2). The article is expected to be included in the September issue of the journal.

​TITLE : PyIgH : A unified architecture of IgH EtherCAT Master based on Python considering hard real-time constraints

DOI :  https://doi.org/10.1016/j.micpro.2024.105085

ABSTRACT : The increasing demand for rapid application development tools, especially those employing high-level languages such as Python, has underscored the importance of utilizing a wide array of popular libraries while addressing real-time constraints in distributed hardware systems. This paper introduces PyIgH, a unified architecture of an IgH EtherCAT master based on Python, specifically designed to satisfy hard real-time requirements in an EtherCAT network. Implemented as a Python module, PyIgH exposes the functionalities and capabilities of an open-source EtherCAT master, facilitating seamless configuration and control of EtherCAT slave devices within the Python runtime environment. Real-time adaptation of the POSIX library, encapsulated within Python, is also utilized to satisfy the timing requirements of EtherCAT. The feasibility of the proposed approach is verified by analyzing the real-time performance in terms of periodicity and in-controller delay of the EtherCAT control task with a 1 kHz cycle. Experimental results demonstrate that PyIgH is suitable for hard real-time applications and serves as a valid alternative to conventional low-level EtherCAT masters. Additionally, a practical application involving motion control of a six-axis collaborative robot showcases consistent performance of PyIgH within a real-time multi-tasking environment.